LDMOS transistor structures are widely used as semiconductor devices for many types of transistor applications such as high voltage MOS field effect transistors. An LDMOS transistor comprises a lightly doped drain region to enhance the breakdown voltage. LDMOS transistors are, however, limited in their high frequency performance due to the feedback capacitance Cdg between the gate and the drain. FIG. 1 shows one type of an LDMOS transistor as known in the art. A wafer comprises for example a p+ substrate 1 with an epitaxial layer 12 which includes n-type areas 2 and 3 implanted on the surface to provide a drain and source region, respectively. The backside of the substrate 1 comprises a wafer backside metal layer 9 which can be made of gold or aluminum and is used for grounding and source contact purposes. The epitaxial layer 12 is usually covered with an insulator layer 8 such as silicon oxide in which a polysilicon or silicide gate 4 is arranged to cover the channel between the drain 2 and source 3. On top of this layer is usually a passivation layer 11. Depending on the technology, the source 3 in this exemplary LDMOS transistor may be surrounded by a p-well 5. Electrodes 6 and 7 made of gold or aluminum or any other suitable metal reach through the insulating layer 8 to provide ground and drain potential for the LDMOS device.
To generally reduce a feedback capacitance, it is known to extend the source runner 6 to cover the gate 4 as shown in FIG. 1. Such a so called field plate over the gate 4 effectively decouples the gate drain capacitance Cgd between the gate and the drain but not the gate source capacitance Cgs between the gate and the source runners. In addition, a higher source drain capacitance is created. Furthermore, grounding of the source is needed. To this end, a p+ source implant 10 is provided in a conventional LDMOS transistor. Such a so-called p+ sinker 10 can be created by ion implantation. Effectively, this p+ sinker merges with the p well area 5 and, thus, reaches from the source contact 6 to the backside metal layer 9. As the backside metal layer is grounded, the p+ sinker 10 provides for a connection between the source electrode 6 and ground. This type of connection generates a considerable amount of source resistance which further limits the device's high frequency performance.